1. Field of the Invention
The disclosed embodiments of the present invention relate to memory, and more particularly, to a memory architecture which divides a memory cell array into a plurality of memory banks operating independently of each other.
2. Description of the Prior Art
In order to implement a layout of high density memory cells, a dynamic random access memory (DRAM) needs sufficient row transition time (row cycle time (tRC), which is usually longer than 30 ns). However, the row transition time greatly affects random access cycle time of the DRAM.
One conventional method is to employ an architecture having multiple sets of banks, wherein the architecture can select respective word lines of different banks in parallel and access data of different banks in sequence. However, as different banks need respective word line decoding circuits and respective control circuits, the architecture having multiple sets of banks causes increased areas and costs of memory dies.